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rev 1.0 6/21/00 characteristics subject to change without notice. 1 of 18 www.xicor.com preliminary information programmable analog X9438 dual digitally controlled potentiometer (xdcp ) with operational ampli?r features two cmos voltage operational ampli?rs two digitally controlled potentiometers can be combined or used separately ampli?rs: low voltage operation v+/v- = ?.7v to ?.5v rail-to-rail cmos performance 1mhz gain bandwidth product digitally controlled potentiometers dual 64 tap potentiometers ? total = 10k ? 2-wire serial interface ? cc = 2.7v to 5.5v description the X9438 is a monolithic cmos ic that incorporates two operational ampli?rs and two nonvolatile digitally controlled potentiometers. the ampli?rs are cmos differential input voltage operational ampli?rs with near rail-to-rail outputs. all pins for the two ampli?rs are brought out of the package to allow combining them with the potentiometers, or using them as com- plete stand-alone ampli?rs. the digitally controlled potentiometers consist of a series string of 63 polycrystalline resistors that behave as standard integrated circuit resistors. the two-wire serial port, common to both pots, allows the user to program the connection of the wiper output to any of the resistor nodes in the series string. the wiper posi- tion is saved in the on board e2 memory to allow for nonvolatile restoration of the wiper position. a wide variety of applications can be implemented using the potentiometers and the ampli?rs. a typical application is to implement the ampli?r as a wiper buffer in circuits that use the potentiometer as a voltage reference. the potentiometer can also be combined with the ampli?r yielding a digitally programmable gain ampli?r or programmable current source. block diagram v out1 control and scl sda a3 a2 a1 a0 + memory wp v cc v ni0 v+ v r w0 v ss v out0 + v ni1 v inv1 v inv0 r h0 r l0 r w1 r l1 r h1 wcr1 wcr0
X9438 ?preliminary information characteristics subject to change without notice. 2 of 18 rev 1.0 6/21/00 www.xicor.com pin descriptions host interface pins serial clock (scl) the scl input is used to clock data into and out of the X9438. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with any number of open drain or open col- lector outputs. an open drain output requires the use of a pull-up resistor. device address (a 0 ? 3 ) the address inputs are used to set the least signi?ant 4 bits of the 8-bit slave address. a match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9438. a maximum of 16 devices may share the same 2-wire serial bus. potentiometer pins (1) r h (r h0 ? h1 ), r l (r l0 ? l1 ) the r h and r l inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. r w (r w0 ? w1 ) the wiper output is equivalent to the wiper output of a mechanical potentiometer. amplifier and device pins amplifier input voltage v ni (0,1) and v inv (0,1) v ni and v inv are inputs to the noninverting (+) and inverting (-) inputs of the operational ampli?rs. amplifier output voltage v out (0,1) v out is the voltage output pin of the operational ampli?r. hardware write protect input wp the wp pin, when low, prevents non-volatile writes to the wiper counter registers. note: (1) alternate designations for r h , r l , r w are v h , v l , v w analog supplies v+, v- the analog supplies v+, v- are the supply voltages for the xdcp analog section and the operational ampli?rs. system supply v cc and ground v ss . the system supply v cc and its reference v ss is used to bias the interface and control circuits. pin configuration pin names symbol description scl serial clock sda serial data a0-a3 device address r h0 ? h1 , r l0 ? l1 potentiometers (terminal equivalent) r w0 ? w1 potentiometers (wiper equivalent) v ni(0,1) , v inv(0,1) amplifier input voltages v out0, v out1 amplifier outputs wp hardware write protection v+,v- analog and voltage amplifier supplies v cc system/digital supply voltage v ss system ground nc no connection v cc r l0 r h0 wp sda a1 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 v+ v out0 v ni0 v inv0 a0 nc a 3 scl v inv1 v ni1 soic X9438 v ss r w0 14 13 11 12 a 2 r l1 r h1 r w1 v out1 v- v- v inv0 v ni0 a 3 nc scl 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 wr a 2 v cc r w0 tssop X9438 v+ v out0 14 13 11 12 a 0 v out1 v ni1 v inv1 r l0 r h0 v ss r w1 r h1 r l1 a 1 sda
X9438 ?preliminary information characteristics subject to change without notice. 3 of 18 rev 1.0 6/21/00 www.xicor.com principles of operation the X9438 is an integrated microcircuit incorporating two resistor arrays, two operational ampli?rs and their associated registers and counters; and the serial inter- face logic providing direct communication between the host and the digitally controlled potentiometers and operational ampli?rs. serial interface the X9438 supports a bidirectional bus oriented proto- col. the protocol de?es any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always initiate data transfers and pro- vide the clock for both transmit and receive operations. therefore, the X9438 will be considered a slave device in all applications. clock and data conventions data states on the sda line can change only during scl low periods (t low ). sda state changes during scl high are reserved for indicating start and stop conditions. start condition all commands to the X9438 are preceded by the start condition, which is a high to low transition of sda while scl is high (t high ). the X9438 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condi- tion is met. stop condition all communications must be terminated by a stop con- dition, which is a low to high transition of sda while scl is high. acknowledge acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. the transmitting device, either the master or the slave, will release the sda bus after transmitting eight bits. the master generates a ninth clock cycle and dur- ing this per iod the receiver pulls the sda line low to acknowledge that it successfully received the eight bits of data. the X9438 will respond with an acknowledge after rec- ognition of a start condition and its slave address and once again after successful receipt of the command byte. if the command is followed by a data byte the X9438 will respond with a ?al acknowledge. operational amplifier the voltage operational ampli?rs are cmos rail-to- rail output general purpose ampli?rs. they are designed to operate from dual (? power supplies. the ampli?rs may be con?ured like any standard ampli- ?r. all pins are externally available to allow connec- tions with the potentiometers or as stand alone ampli?rs. potentiometer/array description the X9438 is comprised of two resistor arrays and two operational ampli?rs. each array contains 63 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the ?ed terminals of a mechanical potentiometer (r h and r l inputs). at both ends of each array and between each resistor segment is a cmos switch connected to the wiper (r w ) output. within each individual array only one switch may be turned on at a time. these switches are controlled by a volatile wiper counter register (wcr). the six bits of the wcr are decoded to select, and enable, one of sixty-four switches. the wcr may be written directly, or it can be changed by transferring the contents of one of four associated data registers into the wcr. these data registers and the wcr can be read and written by the host system. instructions and programming device addressing following a start condition the master must output the address of the slave it is accessing. the most signi? cant four bits of the slave address are the device type identi?r (refer to figure 1). for the X9438 this is ?ed as 0101[b]. figure 1. address/identification byte format 1 00 a3 a2 a1 a0 device type identifier device address 1
X9438 ?preliminary information characteristics subject to change without notice. 4 of 18 rev 1.0 6/21/00 www.xicor.com the next four bits of the slave address are the device address. the physical device address is de?ed by the state of the a 0 ? 3 inputs. the X9438 compares the serial data stream with the address input state; a suc- cessful compare of all four address bits is required for the X9438 to respond with an acknowledge. the a 0 a 3 inputs can be actively driven by cmos input signals or tied to v cc or v ss . acknowledge polling the disabling of the inputs, during the internal non-vol- atile write operation, can be used to take advantage of the typical 5ms eeprom write cycle time. once the stop condition is issued to indicate the end of the non- volatile write command the X9438 initiates the internal write cycle. ack polling (flow 1) can be initiated imme- diately. this involves issuing the start condition fol- lowed by the device slave address. if the X9438 is still busy with the write operation no ack will be returned. if the X9438 has completed the write operation an ack will be returned and the master can then proceed with the next operation. flow 1. ack polling sequence instruction structure the byte following the address contains the instruction and register pointer information. the four most signi? cant bits are the instruction. the next four bits point to one of the two pots and when applicable they point to one of the four wcrs associated data registers. the format is shown below in figure 2. figure 2. instruction byte format the four high order bits de?e the instruction. the next two bits (r1 and r0) select one of the two registers that is to be acted upon when a register oriented instruction is issued. the last bit (p0) selects which one of the two potentiometers is to be affected by the instruction. four of the nine instructions end with the transmission of the instruction byte. the basic sequence is illus- trated in figure 3. these two-byte instructions exchange data between the wiper counter register and one of the data registers. a transfer from a data regis- ter to a wiper counter register is essentially a write to a static ram. the response of the wiper to this action will be delayed t wrl . a transfer from the wiper counter reg- ister (current wiper position) to a data register is a write to non-volatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the two potentiometers and one of its associated registers; or it may occur globally, wherein the transfer occurs between all of the potentiometers and one of their associated registers. four instructions require a three-byte sequence to complete. the basic sequence is illustrated in figure 4. these instructions transfer data between the host and the X9438; either between the host and one of the data registers or directly between the host and the wiper counter and analog control registers. these instruc- tions are: 1) read wiper counter register or read the current wiper position of the selected pot, 2) write wiper counter register, i.e. change current wiper posi- tion of the selected pot; 3) read data register, read the contents of the selected non-volatile register; 4) write data register, write a new value to the selected data register. the bit structures of the instructions are shown in figure 6. nonvolatile write command completed enter ack polling issue start issue slave address ack returned? further operation? issue instruction issue stop no yes yes prooceed issue stop no prooceed i1 i2 i3 i0 r1 r0 0 p0 wcr select register select instructions
X9438 ?preliminary information characteristics subject to change without notice. 5 of 18 rev 1.0 6/21/00 www.xicor.com figure 3. two-byte command sequence figure 4. three-byte command sequence s t a r t 0101a3a2a1a0 a c k i3 i2 i1 i0 r1 r0 0 p0 a c k scl sda s t o p s t a r t 0 1 0 1 a3 a2 a1 a0 a c k i3 i2 i1 i0 0 p0 r1 r0 a c k scl sda s t o p a c k d5 d4 d3 d2 d1 d0 the increment/decrement command is different from the other commands. once the command is issued and the X9438 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a ?e tuning capability to the host. for each scl clock pulse (t high ) while sda is high, the selected wiper will move one resistor segment towards the v h terminal. similarly, for each scl clock pulse while sda is low, the selected wiper will move one resistor segment towards the v l terminal. a detailed illustration of the sequence for this operation is shown in figure 5. figure 5. increment/decrement command sequence s t a r t 0101a3a2a1a0 a c k i3 i2 i1 i0 p1 p0 r1 r0 a c k scl sda s t o p x x i n c 1 i n c 2 i n c n d e c 1 d e c n
X9438 ?preliminary information characteristics subject to change without notice. 6 of 18 rev 1.0 6/21/00 www.xicor.com figure 6. instruction set read wiper counter register (wcr) read the contents of the wiper counter register p 0 . p0: 0-wcr0, 1-wcr1 write wiper counter register (wcr) write new value to the wiper counter register p 0 . p0: 0-wcr0, 1-wcr1 read data register (dr) read the contents of the register pointed to by p 0 and r 1 -r 0 . r1 r0: 00-r0, 10-r1 01-r2, 11-r3 write data register (dr) write new value to the register pointed to by p 0 and r 1 -r 0 . definitions: sack ?slave acknowledge, mack ?master acknowledge, i/d ?increment/decrement (1/0), r ?register, p ?potentiometer s t a r t device type identifier device addresses s a c k instruction opcode wcr addresses s a c k register data (sent by slave on sda) m a c k s t o p 0101 a 3 a 2 a 1 a 0 1001000 p 0 00 d 5 d 4 d 3 d 2 d 1 d 0 s t a r t device type identifier device addresses s a c k instruction opcode wcr addresses s a c k register data (sent by master on sda) s a c k s t o p 0101 a 3 a 2 a 1 a 0 1010000 p 0 00 d 5 d 4 d 3 d 2 d 1 d 0 s t a r t device type identifier device addresses s a c k instruction opcode wcr/dr addresses s a c k register data (sent by master on sda) m a c k s t o p 0101 a 3 a 2 a 1 a 0 1011 r 1 r 0 0 p 0 00 d 5 d 4 d 3 d 2 d 1 d 0 s t a r t device type identifier device addresses s a c k instruction opcode wcr/dr addresses s a c k register data (sent by master on sda) s a c k s t o p high-voltage write cycle 0101 a 3 a 2 a 1 a 0 1100 r 1 r 0 0 p 0 00 d 5 d 4 d 3 d 2 d 1 d 0
X9438 ?preliminary information characteristics subject to change without notice. 7 of 18 rev 1.0 6/21/00 www.xicor.com figure 6. instruction set (continued) transfer data register to wiper counter register transfer the contents of the register pointed to by r 1 -r 0 to the wcr pointed to by p 0 . transfer wiper counter register to data register transfer the contents of the wcr pointed to by p 0 to the register pointed to by r 1 -r 0 . global transfer data register to wiper counter register transfer the contents of all four data registers pointed to by r 1 -r 0 to their respective wcr. global transfer wiper counter register to data register transfer the contents of all wcrs to their respective data registers pointed to by r 1 -r 0 . increment/decrement wiper counter register enable increment/decrement of the wcr pointed to by p 0 . p0: 0 or 1 only. s t a r t device type identifier device addresses s a c k instruction opcode wcr/dr addresses s a c k s t o p 0101 a 3 a 2 a 1 a 0 1101 r 1 r 0 0 p 0 s t a r t device type identifier device addresses s a c k instruction opcode wcr/dr addresses s a c k s t o p high-voltage write cycle 0101 a 3 a 2 a 1 a 0 1110 r 1 r 0 0 p 0 s t a r t device type identifier device addresses s a c k instruction opcode dr addresses s a c k s t o p 0101 a 3 a 2 a 1 a 0 0001 r 1 r 0 00 s t a r t device type identifier device addresses s a c k instruction opcode dr addresses s a c k s t o p high-voltage write cycle 0101 a 3 a 2 a 1 a 0 1000 r 1 r 0 00 s t a r t device type identifier device addresses s a c k instruction opcode wcr addresses s a c k increment/decrement (sent by master on sda) s t o p 0101 a 3 a 2 a 1 a 0 0010000 p 0 i/ d i/ d .... i/ d i/ d
X9438 ?preliminary information characteristics subject to change without notice. 8 of 18 rev 1.0 6/21/00 www.xicor.com register operation both digitally controlled potentiometers share the serial interface and share a common architecture. each potentiometer is associated with a wiper counter reg- ister (wcr), and four data registers. figure 7 illus- trates the control, registers, and system features of the device. figure 7. system block diagram wiper counter (wcr) and analog control registers (acr) the X9438 contains two wiper counter registers, one for each xdcp. the wiper counter register is equivalent to a serial-in, parallel-out counter, with its outputs decoded to select one of sixty-four switches along its resistor array. the contents of the wiper counter register can be altered in four ways: it may be written directly by the host via the write wcr instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers (dr) via the xfr data register instruction (parallel load); it can be modi?d one step at a time by the increment/decrement instruc- tion (wcr only). finally, it is loaded with the contents of its data register zero (r0) upon power-up. the wiper counter register is a volatile register; that is, its contents are lost when the X9438 is powered-down. although the registers are automatically loaded with the value in r0 upon power-up, it should be noted this may be different from the value present at power-down. data registers (dr) each potentiometer has four non-volatile data registers (dr). these can be read or written directly by the host and data can be transferred between any of the four data registers and the wcr. it should be noted all operations changing data in one of these registers is a non-volatile operation and will take a maximum of 10ms. if the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could store sys- tem parameters or user preference data. register descriptions and memory map memory map wiper counter register (wcr) wp0-wp5 identify wiper position. data registers (dr, r0-r3) v out (0,1) (dr0-dr3) 0,1 interface and control circuitry scl sda a0 a1 a2 a3 v h (0,1) v l (0,1) wp v w (0,1) v ni (0,1) + wcr 0,1 v inv (0,1) wcro wcr1 dr0 dr0 dr1 dr1 dr2 dr2 dr3 dr3 0 0 wp5 wp4 wp3 wp2 wp1 wp0 (volatile) (lsb) wiper position or user data (nonvolatile)
X9438 ?preliminary information characteristics subject to change without notice. 9 of 18 rev 1.0 6/21/00 www.xicor.com absolute maximum ratings temperature under bias ................... ?5? to +135? storage temperature ........................ ?5? to +150? voltage on sda, scl or any address input with respect to v ss .........................?v to +7v voltage on any v+ (referenced to v ss ) ................. +7 v voltage on any v- (referenced to v ss ) ................... -7v (v+) ?(v-) ............................................................. 10v any r h .................................................................... v+ any r l ...................................................................... v- lead temperature (soldering, 10 seconds)........ 300? comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this speci?ation) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions temperature min. max. commercial 0 c +70 c industrial ?0 c +85 c device supply voltage (v cc ) limits X9438 5v 10% X9438-2.7 2.7v to 5.5v potentiometer characteristics (over recommended operating conditions unless otherwise stated.) notes: (1) absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position whe n used as a potentiometer. (2) relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti- ometer. it is a measure of the error in step size. (3) mi = rtot/63 or (r h ? l )/63, single pot (=lsb) (4) individual array resolutions symbol parameter limits test conditions min. typ. max. unit r total end to end resistance ?0 +20 % power rating 50 mw 25 c, each pot i w wiper current ? +3 ma r w wiper resistance 40 100 ? v cc = 5v, wiper current = 3ma 100 250 ? v cc = 2.7, wiper current = 1ma vv+ voltage on v+ pin X9438 +4.5 +5.5 v X9438-2.7 +2.7 +5.5 vv- voltage on v- pin X9438 -5.5 -4.5 v X9438-2.7 -5.5 -2.7 v term voltage on any r h or r l pin v- v+ v noise -100 dbv ref: 1v resolution (4) 1.6 % absolute linearity (1) ? +1 mi (3) v w(n)(actual) ? w(n)(expected) relative linearity (2) ?.2 +0.2 mi (3) v w(n + 1) ?v w(n) + mi ] temperature coefficient of r total 300 ppm/ c ratiometric temperature coefficient ?0 ppm/?
X9438 ?preliminary information characteristics subject to change without notice. 10 of 18 rev 1.0 6/21/00 www.xicor.com amplifier electrical characteristics (over the recommended operating conditions unless otherwise speci?d.) v+ and v- ( 5v to 3v) are the ampli?r power supplies. the ampli?rs are speci?d with dual power supplies. v cc and v ss is the logic supply. all ratings are over the temperature range for the industrial (-40 to + 85?) and commercial (0 to 70?) versions of the part unless speci?d differently. system/digital d.c. operating characteristics (over the recommended operating conditions unless otherwise speci?d.) symbol parameter condition industrial commercial unit min. typ. max. min. typ. max. v os input offset voltage v+/v- 3v to 5v 1 3 1 2 mv tc vos input offset voltage temp. coefficient v+/v- 3v to 5v -10 -10 ?/? i b input bias current v+/v- 3v to 5v 50 50 pa i os input offset current v+/v- 3v to 5v 25 25 pa cmrr common mode rejection ratio v cm = -1v to +1v 70 70 db psrr power supply rejection ratio v+/v- 3v to 5v 70 70 db v cm input common mode voltage range t j = 25? v- v+ v- v+ v a v large signal voltage gain v o = -1v to + 1v 30 50 30 50 v/mv v o output voltage swing v- v+ +0.1 -.15 +0.1 -.15 v v i o output current v+/v- = 5.5v v+/v- = 3.3v 50 30 50 30 ma ma i s supply current v+/v- = 5.0v 3 3 ma v+/v- = 3.0v 1.5 1.5 ma gb gain-bandwidth prod r l = 100k, c l = 50pf 1.0 1.0 mhz sr slew rate r l = 100k, c l = 50pf 1.5 1.5 v/?ec m phase margin r l = 100k, c l = 50pf 80 80 deg. symbol parameter limits test conditions min. typ. max. unit i cc v cc supply current (active) 400 ? f scl = 400khz, sda = open, other inputs = v ss i sb v cc current (standby) 1 a scl = sda = v cc , addr. = v ss i li input leakage current 10 ? v in = v ss to v cc i lo output leakage current 10 ? v out = v ss to v cc v ih input high voltage v cc x 0.7 v cc + 0.5 v v il input low voltage ?.5 v cc x 0.1 v v ol output low voltage 0.4 v i ol = 3ma
X9438 ?preliminary information characteristics subject to change without notice. 11 of 18 rev 1.0 6/21/00 www.xicor.com endurance and data retention capacitance power-up timing and sequence a.c. test conditions note: (1) applicable to recall and power consumption applications parameter min. unit minimum endurance 100,000 data changes per bit per register data retention 100 years symbol test typical unit test conditions c i/o input/output capacitance (sda) 8 pf v i/o = 0v c in input capacitance (a0, a1, a2, a3, and scl) 6 pf v in = 0v c l | c h | c w potentiometer capacitance 10/10/25 pf see spice model power up sequence (1) : (1) v cc (2) v+ and v power down sequence: no limitation input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 equivalent a.c. load circuit spice macro model 5v 1533 ? 100pf sda output 2.7v 100pf c w r total r h r l c h r w c l
X9438 ?preliminary information characteristics subject to change without notice. 12 of 18 rev 1.0 6/21/00 www.xicor.com timing diagrams start and stop timing g input timing output timing dcp timing (for all load instructions) t su:sta t hd:sta t su:sto scl sda t r (start) (stop) t f t r t f scl sda t high t low t cyc t hd:dat t su:dat t buf scl sda t dh t aa scl sda vwx (stop) lsb t wrl
X9438 ?preliminary information characteristics subject to change without notice. 13 of 18 rev 1.0 6/21/00 www.xicor.com dcp timing (for increment/decrement instruction) write protect and device address pins timing scl sda vwx t wrid wiper register address inc/dec inc/dec sda scl ... ... ... wp a0, a1 a2, a3 t su:wpa t hd:wpa (start) (stop) (any instruction)
X9438 ?preliminary information characteristics subject to change without notice. 14 of 18 rev 1.0 6/21/00 www.xicor.com ac timing high-voltage write cycle timing dcp timing note: (4) v cc = 5v/2.7v v cc ramp (sample tester) symbol parameter min. max. unit f scl clock frequency 400 khz t cyc clock cycle time 2500 ns t high clock high time 600 ns t low clock low time 1300 ns t su:sta start setup time 600 ns t hd:sta start hold time 600 ns t su:sto stop setup time 600 ns t su:dat sda data input setup time 100 ns t hd:dat (4) sda data input hold time 0/30 ns t r scl and sda rise time 300 ns t f scl and sda fall time 300 ns t aa scl low to sda data output valid time 100 900 ns t dh sda data output hold time 50 ns t i noise suppression time constant at scl and sda inputs 50 ns t buf bus free time (prior to any transmission) 1300 ns t su:wpa wp , a0, a1, a2 and a3 setup time 0 ns t hd:wpa wp , a0, a1, a2 and a3 hold time 0 ns symbol parameter typ. max. unit t wr high-voltage write cycle time (store instructions) 5 10 ms symbol parameter min. max. unit t wrl wiper response time after instruction issued (all load instructions) 10 ? symbol parameter typ. max. unit trv cc v cc power?p rate .2 50 v/ms
X9438 ?preliminary information characteristics subject to change without notice. 15 of 18 rev 1.0 6/21/00 www.xicor.com basic applications function generator + r 2 + r 1 } } r a r b frequency r 1 , r 2 , c amplitude r a , r b c attenuator + v s v o r 3 r 1 v o = g v s -1/2 g +1/2 r 2 r 4 r 1 = r 3 = r 4 r 2 = 2r 1 i to v converter + r 3 r 1 r 2 v o v o /i s = -r 3 (1 + r 2 /r 1 ) + r 2 phase shifter + v s v o c r 1 v o /v s = 1802tan -1 wrc r 1 r + + 2r r r r 1 r v s a 1 a 2 v o = |v s | absolute value amplifier with gain r 1 r v o
X9438 ?preliminary information characteristics subject to change without notice. 16 of 18 rev 1.0 6/21/00 www.xicor.com packaging information 0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) 0.014 (0.35) 0.020 (0.50) pin 1 pin 1 index 0.050 (1.27) 0.598 (15.20) 0.610 (15.49) 0.003 (0.10) 0.012 (0.30) 0.092 (2.35) 0.105 (2.65) (4x) 7 24-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.420" 0.050" typical 0.050" typical 0.030" typical 24 places footprint 0.010 (0.25) 0.020 (0.50) 0.015 (0.40) 0.050 (1.27) 0.009 (0.22) 0.013 (0.33) 0??8 x 45
X9438 ?preliminary information characteristics subject to change without notice. 17 of 18 rev 1.0 6/21/00 www.xicor.com packaging information note: all dimensions in inches (in parentheses in millimeters) 24-lead plastic, tssop package type v .169 (4.3) .177 (4.5) .252 (6.4) bsc .026 (.65) bsc .303 (7.70) .311 (7.90) .002 (.06) .005 (.15) .047 (1.20) .0075 (.19) .0118 (.30) see detail ? .031 (.80) .041 (1.05) .010 (.25) .020 (.50) .030 (.75) gage plane seating plane detail a (20x) (4.16) (7.72) (1.78) (0.42) (0.65) all measurements are typical 08
X9438 ?preliminary information characteristics subject to change without notice. 18 of 18 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, and xd cp are also trademarks of xicor, inc. all others belong to their respective owners. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ?icor, inc. 2000 patents pending rev 1.0 6/21/00 www.xicor.com ordering information device v cc limits blank = 5v ?0% ?.7 = 2.7 to 5.5v temperature range blank = commercial = 0? to +70? i = industrial = ?0? to +85? package p24 = 24-lead plastic dip s24 = 24-lead soic v24 = 24-lead tssop potentiometer organization pot 0 pot 1 w = 10k ? 10k ? y = 2.5k ? 2.5k ? X9438 p t v y

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